1. Field of the Invention
The present invention relates to digital signal buffer circuits, and in particular, to complementary metal oxide semiconductor field effect transistor ("C-MOSFET") circuits for buffering transistor-transistor logic ("TTL") level signals.
2. Description of the Related Art
Digital signal buffer circuits are commonly used for such purposes as signal or circuit isolation, impedance matching, or improvement of circuit fan-in and fan-out characteristics. A common type of buffer circuit design is an inverter circuit.
Referring to FIG. 1, a conventional inverting buffer circuit often uses complementary MOSFETs Qa, Qb, Qc, Qd. Signal inversion is performed by P-type MOSFET ("P-MOSFET") Qc and enhancement mode N-type MOSFET ("N-MOSFET") Qd which are mutually coupled in a totem-pole configuration. The gates of MOSFETs Qc and Qd are connected together and pulled up by enhancement mode N-MOSFET Qa and depletion mode N-MOSFET Qb which are mutually coupled in a totem-pole configuration. The pull-up MOSFETs Qa and Qb, because of their drain-gate and gate-source connections, respectively, act as a resistive pull-up for the gates of the inverter MOSFETs Qc and Qd. Typical MOSFET channel parameters for the buffer circuit of FIG. 1 are as shown below in Table 1.
TABLE 1 ______________________________________ (FIG. 1 [PRIOR ART]) MOSFET CHANNEL WIDTH CHANNEL LENGTH (TYPE) (MICRONS [.mu.]) (MICRONS [.mu.]) ______________________________________ Qa (N enh.) 30 8 Qb (N depl.) 4 8 Qc (P) 50 1.2 Qd (N enh.) 190 1.2 ______________________________________
Referring to FIG. 2, an alternative conventional MOSFET buffer circuit includes P-MOSFETs Qe and Qh, and enhancement mode N-MOSFETs Qf, Qg and Qi, interconnected as shown. The pull-up MOSFET Qe and the parallel combination of pull-down MOSFETs Qf and Qg are coupled in a totem-pole configuration as one inverter, with pull-up MOSFET Qh and pull-down MOSFET Qi comprising another inverter. Together, these inverters buffer the input signal and produce an in-phase output signal. Typical MOSFET channel parameters for the buffer circuit of FIG. 2 are as shown below in Table 2.
TABLE 2 ______________________________________ (FIG. 2 [PRIOR ART]) MOSFET CHANNEL WIDTH CHANNEL LENGTH (TYPE) (MICRONS [.mu.]) (MICRONS [.mu.]) ______________________________________ Qe (P) 60 1.3 Qf (N enh.) 120 1.3 Qg (N enh.) 30 1.3 Qh (p) 90 1.0 Qi (N enh.) 80 1.0 ______________________________________
While the foregoing exemplary conventional buffer circuits are satisfactory for many applications, one operating characteristic in particular has become increasingly problematic, namely, DC power consumption for TTL-to-CMOS signal level conversion. The need for a low power digital signal buffer circuit has become more critical as the total number of input/output ("I/O") pins on many integrated circuits increases. In other words, as more and more input and output signals must be buffered, total DC power consumption becomes increasingly significant.
Typical DC current drain from the power supply VDD (=VCC for TTL operation) for the buffer circuits shown in FIGS. 1 and 2, with the input signal level at a TTL logic high of approximately 2 volts, is approximately 3-5 milliamperes ("mA"), depending upon the actual power supply voltage (VCC) and ambient temperature. When upwards of 20 I/O ports are active, the total DC current, and therefore DC power, consumption becomes significant--even for only the buffer circuits. It would be desirable to have a low power digital signal buffer circuit design in which this DC current drain is significantly reduced.